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    • 专利摘要:
    A method of manufacturing a semiconductor device cell (46) on a surface of a silicon carbide (SiC) semiconductor layer, comprising the formation of a segmented source and body contact (CSSC) (22) of the semiconductor device cell (46) over the surface of the SiC semiconductor layer. The CSSC (22) comprises a body contact segment (22A) disposed over the surface of the semiconductor layer and close to a body contact area of the semiconductor device cell (46), the segment body contact member (22A) disposed substantially disposed over the center of the semiconductor device cell (46). The SCCS (22) also includes at least one source contact segment (22B) disposed over the surface of the semiconductor layer and close to a source contact area of the semiconductor device cell (46). the source contact segment (s) (22B) only partially surrounding the body contact segment (22A) of the SCCS (22).
    公开号:FR3022685A1
    申请号:FR1555620
    申请日:2015-06-19
    公开日:2015-12-25
    发明作者:Alexander Viktorovich Bolotnikov；Peter Almern Losee
    申请人:General Electric Co；
    IPC主号:
    专利说明:

    [0001] The present invention relates to semiconductor devices such as silicon carbide (SiC) power devices, including field effect transistors (eg MOSFETs, DMOSFETs, UMOSFETs, VMOSFETs, etc.). .), insulated gate bipolar transistors (IBGTs), isolated base MOS control thyristors (IBMCT), junction field effect transistors (JFETs), and metal-semiconductor field effect transistors (MESFETs). We will begin by presenting various aspects of the art that may relate to various aspects of the present invention, which are described and / or claimed later. It is believed that these explanations will be useful for providing reference information facilitating a better understanding of the various aspects of the present invention. In this way, these indications must be read in this light and not as acknowledgments of prior art.
    [0002] Power conversion devices are commonly employed in all modern electrical systems to convert electricity from one form to another for consumption by a load. Many power electronics systems use a variety of semiconductor devices and components such as thyristors, diodes, and various types of transistors (eg, metal-oxide-semiconductor field effect transistors (MOSFETs), field effect transistors junction (JFET), insulated gate bipolar transistors (TBGIs) and other suitable transistors).
    [0003] Particularly for high-frequency, high-voltage and / or high-intensity applications, devices using wide-bandgap semiconductors, such as silicon carbide (SiC), aluminum nitride (A1N), nitride gallium (GaN), etc., can offer a number of advantages from the point of view of high temperature operation, reduced on-state resistance and miniaturization of chips more than in the corresponding silicon (Si) devices. In this way, wide bandgap semiconductor devices have advantages for power conversion applications, for example power distribution systems (eg in power grids), power generation systems, power generation systems, power distribution systems, power distribution systems, power distribution systems, power distribution systems, power distribution systems, energy (eg in solar and wind energy converters, as well as consumer goods (eg electric vehicles, appliances, power supplies, etc.).
    [0004] In one embodiment, a system includes a semiconductor device cell disposed on a surface of a silicon carbide (SiC) semiconductor layer. The semiconductor device cell comprises: a migration zone having a first conductivity type, a well area adjacent to the migration zone and having a second conductivity type, a source area adjacent to the well area and having the first conductivity type, a channel area adjacent to the source area close to the surface and having the second conductivity type, and a body contact area disposed over a portion of the well area and having the second type of conductivity, the body contact area being disposed substantially in the center of the semiconductor device cell. The device cell includes a segmented source and body contact (CSSC) disposed over a portion of the surface, the CSSC comprising: a body contact segment disposed over the body contact area substantially in the center of the semiconductor device cell, and at least one source contact segment disposed in the immediate vicinity of the body contact area and over a portion of the source area, the one or more segment (s) of the source contact not completely surrounding the body contact segment of the SCCS. In one embodiment, a system includes a cellular arrangement of semiconductor devices having a plurality of semiconductor device cells disposed on a surface of a silicon carbide (SiC) semiconductor layer. The different cells of semiconductor cellular devices each comprise: a migration zone having a first conductivity type, a well area adjacent to the migration zone and having a second conductivity type, a source area adjacent to the well area and having the first type of conductivity. The well area of each device cell includes a body contact area disposed close to the surface and the source area of each device cell includes a source contact area disposed near the surface and close to the surface. body contact area. The different semiconductor cell device cells each comprise a symmetrical segmented source and body contact (CSSC) disposed over a portion of the surface, the symmetrical CSSC comprising a body contact segment disposed over the body contact of the semiconductor device cell and at least one source contact segment disposed in the immediate vicinity of the body contact segment and below the source contact area of the semiconductor device cell, the the source contact segment (s) not entirely surrounding the CSSC body contact segment.
    [0005] In one embodiment, a method for manufacturing a semiconductor device cell on a surface of a silicon carbide (SiC) semiconductor layer comprises forming a segmented source and body contact (CSSC). of the semiconductor device cell over the surface of the SiC semiconductor layer. The CSSC comprises a body contact segment disposed over the surface of the semiconductor layer and close to the body contact area of the semiconductor device cell, the body contact segment being disposed substantially beyond the surface of the semiconductor layer. above the center of the semiconductor device cell. The SCCS also includes at least one source contact segment disposed over the surface of the semiconductor layer and close to a source contact area of the semiconductor device cell, the segment (s). source contact only partially surrounding the body contact segment of the SCCS. The invention will be better understood from the detailed study of some embodiments taken by way of nonlimiting examples and illustrated by the appended drawings in which: FIG. 1 is a schematic representation of a planar MOSFET device according to FIG. prior art; FIG. 2 is a schematic view illustrating the resistance for various zones of a MOSFET device according to the prior art; Figure 3A is a top view of a semiconductor device cell having a symmetrical segmented source and body contact area (CSSC) according to embodiments of the present invention; FIG. 3B is a top view of another embodiment of a device cell having a symmetrical CSSC area and having exaggerated manufacturing defects; Figure 3C is a top view of a cellular arrangement of CSSC devices having rectangular cells of devices with symmetrical segmented source and body contacts (CSSCs) according to embodiments of the present invention; FIG. 4 is a sectional view of a portion of the cellular device arrangement embodiment of the CSSC devices shown in FIG. 3C; Figure 5 is a sectional view of another portion of the cellular device arrangement embodiment of the CSSC devices shown in Figure 3C; FIG. 6 is a top view of another embodiment of a cellular arrangement of CSSC devices having staggered rectangular device cells with symmetrical CSSCs; FIG. 7 is a top view of FIGS. another embodiment of a cellular arrangement of CSSC devices having elongate hexagonal device cells with symmetric CSSCs; Figure 8 is a top view of another embodiment of a cellular arrangement of CSSC devices having rectangular device cells with asymmetric CSSCs; 9 is a top view of another embodiment of a cellular arrangement of CSSC devices having hexagonal device cells with asymmetric CSSCs; Figure 10 is a top view of another embodiment of a cellular arrangement of CSSC devices having square device cells with asymmetric CSSCs; Figure 11 is a top view of another embodiment of a cellular arrangement of CSSC devices having hexagonal device cells with asymmetric CSSCs; Figure 12A is a top view of an embodiment of a non-cellular arrangement of band devices including continuous source contact strips and continuous body contact strips; FIG. 12B is a top view of an embodiment of a non-cellular arrangement of ladder-band devices having segmented source / body contact strips; FIG. 12C is a top view of an embodiment of a cellular arrangement of devices including square device cells lacking CSSC; 13 is a graph illustrating the relationships between the normalized channel width (Wch) (normalized along the channel width of the ladder array device arrangement 200 of FIG. 12B) and the width of the JFET area. (WJFET) for embodiments of cellular arrangements of CSSC devices with different channel lengths (Lch); FIG. 14 is a graph illustrating the relationships between the standardized JFET density (DJFET) (normalized to the density of JFET in the ladder-band device arrangement of FIG. 12B) and the width of the JFET zone. (WJFET) for embodiments of cellular arrangements of CSSC devices with different channel lengths (Lch); FIG. 15 is a graph illustrating the relationships between the normalized channel width (WCH) (normalized along the channel width of the cellular arrangement of square-cell devices of FIG. 12C) and the width of the JFET area. (WJFET) for embodiments of cellular arrangements of CSSC devices with different channel lengths (Lch); and FIG. 16 is a graph illustrating the relationships between the standardized JFET density (DJFET) (normalized to JFET density in the cellular arrangement of square-cell devices of FIG. 12C) and the width of the region of FIG. JFET (WJFET) for embodiments of cellular arrangements of CSSC devices with different channel lengths (Lch). One or more specific embodiments will now be described. In order to provide a concise description of these embodiments, not all details of a concrete implementation are described in the specification. During the development of any concrete implementation, especially in a study or design project, many specific decisions of the implementation must be made to achieve the specific goals of the developers such as the respect of constraints related to the system and of a commercial nature, which may vary from one implementation to another. In addition, such development work could be complex and time-consuming, but would nonetheless represent ordinary work of design, manufacture, and manufacture for ordinary specialists benefiting from the present invention. In evoking elements of various embodiments of the present invention, it is to be understood that singular definite and indefinite articles mean that there are one or more of the elements. It is understood that the terms "comprising", "comprising" and "having" are inclusive and mean that there may be additional elements other than the named elements. In addition, the references to "a first embodiment" or "an embodiment" of the present invention are not intended to be construed as excluding the existence of additional embodiments which also include the elements characteristics mentioned. It will be understood that the term "substantially" used herein to describe a shape, position or alignment of an element covers ideal or intended shapes, positions and alignments, as well as imperfectly shaped shapes, positions and alignments. implemented because of the variability of the semiconductor manufacturing process, as can be understood by one skilled in the art. The term "symmetrical" may be used here to qualify a segmented source / body contact area, a segmented source / body contact, or a device cell that has at least two specular planes of symmetry placed perpendicular to the plane of the surface. of the semiconductor. The term "asymmetric" may be used herein to refer to a segmented source / body contact area, a segmented source / body contact, or a device cell that has fewer than two specular planes of symmetry placed perpendicular to the plane of the surface. of the semiconductor. The term "centered" may be used herein to refer to a segmented source / body contact area, a segmented source / body contact, or a device cell in which the body contact area is not substantially centrally disposed. , respectively, of the segmented source / body contact area, the segmented source / body contact, or the device cell. The adjective "off center" or the "non-centered" phrase may be used herein to qualify a segmented source / body contact area, a segmented source / body contact, or a device cell in which the body contact area is not disposed substantially in the center, respectively, of the segmented source / body contact area, the segmented source / body contact, or the device cell. In addition, it will be understood that a semiconductor device cell herein described as being disposed at or "on the surface" of a semiconductor layer includes a semiconductor device cell having portions thereof disposed in the mass. of the semiconductor layer, portions are arranged close to the surface of the semiconductor layer, portions are arranged at the same level as the surface of the semiconductor layer and / or portions are disposed over or above the surface of the semiconductor layer. The field effect transistor (FET) device is one of the cornerstones of modern power electronics.
    [0006] For example, Fig. 1 shows an active cell of an N-channel planar field effect transistor, in this case a DMOSFET, hereinafter referred to as MOSFET device 10. In order to more clearly represent certain components of the MOSFET device 10 As well as other devices discussed below, certain well-known design elements (eg, the metallization top layer, the passivation layer, the edge termination, and the like) can be omitted. The MOSFET device 10 shown in FIG. 1 comprises a semiconductor layer 2 (eg a silicon carbide semiconductor layer) having a first surface 4 and a second surface 6. The semiconductor layer 2 comprises a migration 16 having a first conductivity type (eg, an N-type migration layer 16), a well area 18 adjacent to the migration zone and located close to the first surface, the well area having an second type of conductivity (eg a P 18 well). The semiconductor layer 2 also includes a source area 20 adjacent to the well area 18, the source area having the first conductivity type (eg, the N type source area). A gate insulating layer 24 is disposed on a portion of the first surface 4 of the semiconductor layer 2 and a gate electrode 26 is disposed on the gate insulating layer 24. The second surface 6 of the semiconductor layer 2 is a substrate layer 14 and the drain contact 12 is disposed on the underside of the device 10, along the substrate layer 14. The source / body contact 22 is disposed over the semiconductor layer 2 by partially covering the source area 20 and the well / body areas 18. In operation, a suitable gate voltage (eg equal to or greater than a threshold voltage (VTH) ) of the MOSFET device 10) can cause the formation of an inversion layer in the channel region 28, as well as the strengthening of a conductive path in the junction field effect transistor (JFET) region 29 by as a result of carrier build-up, which allows a current to flow between the contact 22 (i.e., the source electrode) and the drain contact 12. In the MOSFET devices discussed herein, the channel area 28 may be globally defined 15 as an upper part of e the well area P 28 disposed beneath the gate electrode 26 and the gate dielectric 24. As shown in FIG. 2, the various areas of the MOSFET device 10 may each have a corresponding resistance, and a total resistance (e.g. ex. a resistance in the on state, Rds (on)) of the MOSFET device 10 may be represented as a sum of each of these resistors. For example, as shown in FIG. 2, the on-state resistance, Rds (on), of the N-channel MOSFET device 10 can be approximated as a sum of: a resistor Rs 30 (p. eg N + zone resistance and contact resistance 22); a resistor Rch 32 (eg an inversion channel resistor of the area 28 shown in Figure 1); a resistor Ra '34 (eg a resistance of an accumulation layer between the gate oxide 24 and the portion of the migration layer 16 located between the well areas P 18); an RJFET resistor 36 (eg a non-depleted choke zone resistor between the well areas P 18); resistance Rd ft 38 (eg resistance around migration layer 16); and a resistor Rstih 40 (eg resistance around the substrate layer 14). Note that the resistors shown in Figure 2 are not intended to be exhaustive and that other resistors (eg, drain contact resistance, intrinsic resistance, etc.) could potentially be present at the same time. In view of the foregoing, the present embodiments relate to designs and arrangements of cellular devices that improve the performance of semiconductor devices. In particular, in order to reduce or greatly limit on-state conduction losses (eg, to strongly limit Rds (on)), it may be desirable to reduce the resistance of the components of the MOSFET device 10. In In some cases, one or two resistance components can dominate conduction losses, and acting on these factors can have large effects on Rds (on). For example, for devices in which migration resistance 38, substrate resistance 40 and contact resistance 30 are negligible, especially low voltage devices having low mobility in the inverting layer (e.g. (eg SiC devices), channel resistance (Rch 32) may be responsible for a significant portion of the conduction losses of the devices. As such, the present embodiments include designs and arrangements of cellular devices that provide greater channel width and / or channel density to reduce channel resistance (Rch 32) and this is to reduce conduction losses in the on state. In another example, in medium and high voltage devices, the JFET zone resistor (RJFET 36) may be responsible for a significant portion of the total conduction losses of the devices. As such, the present embodiments include designs and arrangements of higher density JFET cellular devices to reduce JFET (RJFET) zone resistance and thereby reduce conduction losses in high and medium voltage devices, as well as in low voltage devices operating at the highest temperatures. In addition, the designs and arrangements of cellular devices described herein may also allow for a decrease in the intrinsic resistance component, which brings a further improvement in device performance. On the other hand, although the present invention can be explained later in the context of SiC MOSFET devices, the present invention is applicable to systems of other types of materials (eg silicon (Si), germanium (Ge), aluminum nitride (A1N), gallium nitride (GaN), gallium arsenide (GaAs), diamond (C) or any other suitable semiconductor), as well as other types of device structures (eg, UMOSFET, VMOSFETs, insulated gate bipolar transistors (TBGIs), isolated base MOS control thyristors (IBMCT), junction field effect transistors (JFETs) ) and the metal-semiconductor field effect transistors (MESFET) or other suitable device using N-channel as well as P-channel designs. As illustrated in FIG. 2, the contacts 22 of the MOSFET device 10, which globally provide an ohmic connection to the source electrode, are arranged above a portion of the N + zone 20 as well as a portion of the well area P or P + body area 18. The contact 22 is generally a metal interface comprising one or more metal layers located between these semiconductor portions of the MOSFET device 10 and the source metal electrode. In particular, the portion of the N + area 20 of the MOSFET device 10 disposed under the contact 22 may here be referred to as the source contact area 42 of the MOSFET device 10. Furthermore, the portion of the well area P or P + 18 body of the MOSFET device 10 which is disposed under the contact 22, which may have a P + doping at a higher level than that of the remainder of the well area P 18, can here be called the body contact zone 44 of the device MOSFET 10. For the sake of homogeneity, the parts of the contact 22 may be designated here according to the part of the semiconductor device which is disposed under the contact 22. For example, the part of the contact 22 disposed above the contact a body contact area 44 can here be referred to as the body contact area 22A of the contact 22. Similarly, the portion of the contact 22 disposed above a source contact area 42 of the MOSFET device 10 can here be called source contact zone 2 2B of the contact 22.
    [0007] In view of the foregoing, FIG. 3A is a top view or plan view of an embodiment of a rectangular semiconductor device cell 46 (eg a MOSFET device cell 46). semiconductor) which can reduce on-conduction losses as set forth above. Note that the final position of the contact 22 of the device cell 46 is represented by transparency (i.e. the dashed rectangle 22) in FIG. 3A to show the layers of the device cell 46 that will be disposed under the contact. 22. For example, the illustrated device cell 46 includes a rectangular body contact area 44 disposed in the middle of the device cell 46. The body contact area 44 of the device cell 42 is surrounded by a N + area which is itself surrounded by an N-channel region 47 of the semiconductor device cell 46. In addition, the illustrated semiconductor device cell 46 includes a junction field effect transistor (JFET) region 48 which surrounds the P channel region 47 of the device cell 46. As illustrated in FIG. 3A, portions of the N + area 20 disposed under the contact 22 serve as segments 42A and 42B of the source contact area 42 of the device cell 46. In this way, the surface of the device cell 46 disposed under the contact 22 (namely the body contact zone 44 as well as the two segments 42A and 42B of the source contact zone 42) can here be generally called a zone Segmented source and body contact contact (CSSC) 50. Similarly, the contact 22, once formed, can here be globally called segmented source and body contact (CSSC) 22. In the CSSC area 50 of the device As shown in FIG. 3A, it should be emphasized that the body contact area 44 is only partially (ie incompletely) surrounded by the portions 42A and 42B of the source contact area 42. That is, in some embodiments, the source contact area 42 (eg, the portions 42A and 42B of the source contact area 42) may be described as being disposed on less than all sides (p. eg the edges, the faces) of the body contact area 44, e.g. In some embodiments, segments of the source contact area 42 may be described as being placed on fewer than six sides, less than five sides, less than four sides, less than three sides, less than two sides, or on one side only of a body contact area 44; or the source contact may be described as being disposed on less than the entire periphery of the body contact area. In addition, the illustrated device cell 46 may be described as having segments 42A and 42B of the source contact area 42 disposed on opposite sides of the body contact area 44. Thus, the SCCS design in accordance with FIG. This embodiment greatly limits the dimensions of the cell and increases the density of the conductive areas (eg, channel areas, JFET, intrinsic) per individual cell. In the embodiment illustrated in Figure 3A, the semiconductor device cell 46, the CSSC area 50 and / or the CSSC 22 may be described as centered and / or symmetrical. For example, the device cell 46, CSSC area 50, and / or CSSC 22 may be referred to as centered because the represented body contact area 44 is disposed in the center of the CSSC area 50 and in the center of the area. cell 46 of semiconductor device. Moreover, once the CSSC 22 is formed, the body contact segment of the CSSC 22 will also be disposed at the center of the device cell 46, over the body contact area 44 shown in Figure 3A. In addition or according to another possibility, the semiconductor device cell 46, the CSSC area 50 and / or the CSSC 22 may be qualified as symmetrical because of a number of planes of symmetry, the planes of symmetry being oriented perpendicularly to the surface of the semiconductor accommodating the device cell 46 (that is, oriented along the z axis, perpendicular to the xy plane). For example, as illustrated in FIG. 3A, the semiconductor device cell 46, the CSSC area 50, and the CSSC 22 have two planes of symmetry oriented along the z axis: the first is an xz plane disposed in the center of the device cell 46 and the second is a plane yz disposed at the center of the device cell 46, both dividing the device cell 46, the CSSC area 50 and the SCCC 22 into two equal parts. Referring to Figure 3B, in some embodiments, the device cell 46 may have less than ideal alignment and / or feature definition due to manufacturing deviations and tolerances.
    [0008] In these embodiments, the intended structure (ie, what was intended to be implemented depending on the design) can be considered here to be centered and / or symmetrical even if the actual structure of the cell 46 The device as manufactured may have irregularities related to the limitations of the manufacturing process. For example, as discussed later with reference to Figure 3B, in some embodiments, the body contact area 44 may be slightly offset from the center of the device cell 46, the CSSC 22 may be not perfectly aligned with the channel area 48, the body contact area 44 may extend a little above or below the CSSC 22, etc. However, the device cell 46 can still be considered as centered and / or symmetrical on the basis of the targeted structure, even if, as it is concretely realized, it may differ from the target structure due to differences induced by the manufacturing process.
    [0009] Figure 3A also shows dimensions of the illustrated device cell 46. For example, Figure 3A shows the channel length (Lch 52), the distance between the channel and the ohmic area (Lch_to_ohp, 54), the the ohmic area (Wohp, 56), the width of the source contact areas (eg W - n 42A 58A and W - n 42B 58B, Wn = Wn 42A + Wn 42B), the width of the contact area. body contact (Wp 60), channel width (W, - ch-Vertical 62A and Wch-Ho izontal 62B; Val = 2W - ch-Vertical + 2Wch-Horizontal, ignoring conduction in angles), the surface of the device cell (represented by the entire area surrounded by the rectangle 46, and the JFET area per individual cell (JFET area 48) for the illustrated device cell 46. In some embodiments the distance between the channel and the ohmic zone (Lch_to_ohm 54) can be defined by a minimum distance allowed by the manufacturing process, i still allows separation between the gate and source electrodes.
    [0010] The final position of the CSSC 22, represented by the dotted rectangle 22 shown in 3A, shows the ideal (e.g., perfect) alignment of the contact 22, as well as the ideal (e.g., perfect) definition of the contacts 22. elements. Thus, in the device 46 of Figure 3A, the length of the contact 22 extends substantially exactly parallel to the length of the N + area 20. In addition, the source contact area 44 of the device cell 46 substantially extends not above or below the CSSC 22. Although the ideal alignment and the ideal shape of the elements are shown to simplify the presentation, the present invention is not limited to these specific shapes, dimensions or alignment. In this way, although ideally or perfectly aligned devices (e.g. target device structures) are generally illustrated and presented here, it should be emphasized that in some embodiments, the SCCS (eg the SCCS 22) of device cells according to the present invention (eg device cells 46) may not have an ideal or perfect alignment, as shown in Fig. 3B, due to permissible tolerances in the manufacturing process.
    [0011] For example, Figure 3B illustrates an embodiment of a device cell 46 according to the present invention which has a less than ideal (e.g., imperfect) alignment of the contact 22, as well as a less than ideal definition. ideal (eg imperfect) elements. As illustrated in Figure 3B, in some embodiments, the length of the CSSC 22 may not be perfectly parallel to the length of the N + area (eg intentionally or unintentionally shifted by 1 °, 2 °, 3 °, 4 ° or 5 ° or more), because of the limitations of alignment techniques used in the manufacture of semiconductors. As shown in FIG. 3B, in some embodiments, the SCCC 22 may extend a little above or below the source contact zone 44 or the source contact zone 44 may be prolonged. slightly above or below the CSSC 22 due to the limitations of the alignment techniques used in semiconductor manufacturing. For example, in some implementations, the CSSC 22 may extend, above and / or below the source contact zone 44, less than about 20% Won., 56 (e.g. the total width of the contact 22), less than about 10% of Wohm 56 or less than about 5% of Wohm 56. Moreover, the shapes illustrated and presented here represent ideal or targeted forms 10 (p eg, rectangles, squares, hexagons, etc.) for the elements (eg, the source contact area 44, the N + area 20, etc.) of the device 46. However, as shown in FIG. 3B, in some implementations these elements may be somewhat modified due to the limitations of semiconductor fabrication techniques (eg photolithography), and may therefore appear to have rounder, smoother or elements generally less well defined than the intended structure used in the design of a device. In this way, the present invention can be applied to both ideal device cells in alignment and shape (e.g. as shown in FIG. 3A) as to device cells that are partially misaligned. and / or lacking a perfect definition of the elements (eg as shown in Figure 3B). Figure 3C is a top view or plan view of an embodiment of a semiconductor surface 70 (eg an SiC semiconductor epitaxial layer) which includes one embodiment of an arrangement Segmented source and body contact device (CSSC) cell 72A, which reduces on-conduction loss as set forth above. The illustrated CSSC cell arrangement 72A includes a number of MOSFET device cells 46, such as the device cell 46 of Figure 3A. In particular, each device cell 46 illustrated in FIG. 3C comprises a segmented source and body contact (CSSC) 22 disposed over underlying segment and body segmented contact areas (not shown) 50 (not shown). . Thus, unlike FIG. 3A, the CSSCs 22 shown in FIG. 3C are illustrated in the form of solids that obscure the aforementioned underlying subsurface areas of segmented source and body contact (CSSC). Each represented CSSC 22 comprises a body contact segment 22A as well as two source contact segments 22B which, in some embodiments, may have the same dimensions (eg be symmetrical) or may have different dimensions ( eg to be asymmetrical). In the devices 46 shown in FIG. 3C, the body contact segment 22A of the CSSCs 22 is only partially (i.e. incompletely) surrounded by the source contact segments 22B of the SCCS 22. Otherwise said, the source contact segments 22B of the CSSCs 22 are shown arranged on less than all sides (eg only two sides) of the body contact segments 22A of the CSSCs 22. For example, in embodiments having CSSCs 22 of different shape, portions of the source contact segments 22B of the CSSCs 22 can be placed on fewer than six sides, less than five sides, less than four sides, less than three sides, less than two sides, or on Only one side of a body contact segment 22A of the SCCCs 22. Figure 3C also shows particular dimensions in the arrangement 72A of the illustrated CSSC devices. For example, FIG. 3C illustrates the width of the JFET area (WJFET73), the horizontal spacing 74 of the device cells, the vertical spacing 75 of the device cells, the area of the individual device cells (Acell 76, represented by the area 3022685 surrounded by the dashed rectangle 76), and the area of the JFETs per individual cells (AJFET 78, represented by the hatched portion 78 of the JFET area 48) in the illustrated embodiment of the arrangement. 72A of devices to CSSC. The term "channel density" (Dchannel) can be used here to refer to the ratio of the perimeter of the channel of a particular device cell to the total area of the device cell. In this way, in the arrangement 72A of devices at the CSSC shown in FIG. 3C, the channel density may be equal to the total periphery of the channel 10 of a device cell 46 divided by the area of the device cell (Acell 76) (eg Dchannel = (2Lch horizontal 2Lch vertical) / Acell). In addition, the term "JFET density" (DJFET) can be used herein to refer to the ratio of the JFET area of a particular device cell to the total area of the device cell 46. In this way, in the arrangement 72A of devices with the CSSC shown in FIG. 3C, the density of JFET can be equal to the area of the JFET per cell (AJFET 78) divided by the total area of a device cell (Acell 76) (eg DJFET = WiFET (vertical spacing + horizontal spacing - WJFET) / Acell).
    [0012] As explained below, the cellular arrangement 72A at CSSC reduces the spacing of the devices and, thus, increases the perimeter of the channel per unit area and / or increases the density of the JFET 48 area for the cells. of MOSFET devices. Figure 4 is a sectional view 90 of a portion of a MOSFET device cell arrangement 72A taken along line IV-IV of Figure 3C. In particular, the sectional view 90 represents a portion of the MOSFET device cell arrangement 72A after the formation of a gate electrode 26, dielectric layers 24 and the SCCC 22. As shown in FIG. 3C, the line IV-IV passes through the body contact segment 22A of the CSSC 22, which is disposed over the body contact zone 44 of the CSSC area 50 of the MOSFET device cell 46, as explained above. with reference to Figure 3A. In this way, in the embodiment shown in FIG. 4, the body contact segment 22A of the CSSC 22 is disposed over (eg physically and electrically in contact with) the body contact area P + 44 in the well area P 18. In the illustrated embodiment, the body contact segment 22A of the CSSC 22 is not disposed over (eg physically and electrically in contact with) the zone N + 20 on the sectional view 90.
    [0013] However, in other embodiments, the body contact segment 22A of the contact 22 may be partially disposed over (eg physically and electrically in contact with) the N + area 20, either unintentionally or because of limitations of the semiconductor manufacturing process.
    [0014] Figure 5 is a sectional view 100 of a MOSFET device cell arrangement 72A of Figure 3C, taken along the V-V line. As in the case of FIG. 4, the sectional view 100 of FIG. 5 shows the MOSFET device cell arrangement 72A after the formation of the gate electrode 26, the dielectric layers 24 and the CSSC 22. As shown in FIG. 3C, the line VV passes through the source contact segment 22B of the CSSC 22, which is disposed over the portion 42A of the source contact area 42 of the CSSC area 50 of the cell 46 of FIG. MOSFET device, as explained above with reference to Figure 3A. In this way, in the embodiment illustrated in FIG. 5, the source contact segment 22B of the CSSC 22 is disposed over (eg physically and electrically in contact with) the N + area 20. Thus, on In the sectional view shown 100, the source contact segment 22B of the CSSC 22 is not disposed over (e.g., physically and electrically in contact with) the well area P 18 or the contact area of the body 44.
    [0015] Figure 6 is a top view or plan view of a semiconductor substrate 70 which includes another embodiment of the arrangement 72B of devices to CSSC. Like the arrangement 72A of devices at the CSSC shown in FIG. 3C, the arrangement 72B of devices at the CSSC shown in FIG. 6 comprises a number of cells 46 of MOSFETs having a CSSC 22, described above, arranged by above an underlying area (not shown) of CSSC 50. Thus, as explained above with reference to FIG. 3A, the CSSC 22 includes a body contact segment 22A disposed over the body contact area. 44 of each device cell 46 and further comprises source contact segments 22B disposed over portions 42A and 42B of the source contact area 42. In addition, the device cells 46 also comprise other elements (eg JFET 48 areas, channel areas 47, N + 20 areas), as explained above. Thus, in the arrangement 72B of the CSSC devices of FIG. 6, disposed under each CSSC 22, the CSSC area 50 has a body contact area 44 surrounded on less than all sides (eg, incompletely surrounded ) by the source contact areas 42A and 42B, as explained above with reference to Figure 3A. Thus, in the arrangement 72B of the CSSC devices shown in FIG. 6, each CSSC 22 has a body contact segment 22A surrounded on less than all sides (eg incompletely circled) by one or more source contact segments 22B. Furthermore, as shown in Figure 6, the device cells 46, the CSSCs 22 and the underlying CSSC area (not shown) of the device arrangement 72B may be termed centered, in that the segment The body contact 22A (and the underlying body contact area) is disposed at the center of the device cells 46. In addition or according to another possibility, these elements may be qualified as symmetrical in that the device cells 46, the CSSCs 22 and the underlying CSSC area (not shown) of the device arrangement 72B have at least two planes of symmetry arranged perpendicularly to the plane of the semiconductor surface (that is to say arranged along the z axis). For example, the represented device cells 46 each comprise at least two planes of symmetry: a first plane of symmetry being the plane zy which divides vertically in two each cell 46 of device and a second plane of symmetry being the plane zx which divides horizontally in two each cell 46 of device. As in the arrangement of devices 72A to the CSSC shown in FIG. 3C, the cells 46 of the MOSFET devices of the arrangement 72B of the CSSC devices shown in FIG. 6 are arranged in rows 110. However, in contrast to FIG. 72C arrangement of devices to CSSC shown in Fig. 3C, each of the rows 110 of cells 46 of MOSFET devices of Fig. 6 is shifted or staggered by a distance 112. Horizontal spacing 111 and vertical spacing 113 The layout 72B of CSSC devices is also illustrated in FIG. 6. The staggered arrangement of FIG. 6 allows reduced electric fields near the angles of the well areas P 18 as well as in the gate oxide 24 placed therein. above the center of the JFET zone, as illustrated in FIGS. 4 and 5. In this way, the staggered arrangement of FIG. 6 may allow an improvement of the locking voltage (BV) and the reliability of s devices in comparison to the arrangement of Figure 3C. Figure 7 is a top view or plan view of a semiconductor substrate 70 which includes another embodiment of the arrangement 72C of devices at CSSC. As the arrangements 72A and B of CSSC devices respectively 3022685 24 illustrated in Figures 3B and 6, the arrangement 72C of devices to CSSC shown in Figure 7 includes a number of cells 118 of MOSFET devices. The horizontal spacing 120 and vertical spacing 123 of the CSSC device arrangement 72C is also illustrated in FIG. 7. In addition, each of the MOSFET device cells 118 includes the above-mentioned SCCS 22, which is above an area of CSSC 50 (as explained above with reference to Figure 3A). Similarly, disposed under each CSSC 22, the CSSC area 50 (not shown) comprises a body contact area 44 surrounded on less than all sides (eg incompletely surrounded) by the source contact areas 42A. and 42B, as explained above with reference to Figure 3A. In addition, as illustrated in Figure 7, the device cells 118, the SCCs 22 and the underlying CSSC area (not shown) of the device arrangement 72C may be termed centered in that the segment the body contact 22A (and the underlying body contact area) is disposed at the center of the device cells 118. In addition or in another possibility, these elements may be said to be symmetrical in that the device cells 118, the SCCs 22 and the underlying CSSC area (not shown) of the device arrangement 72C have minus two planes of symmetry arranged perpendicular to the plane of the surface of the semiconductor (that is to say arranged on the z axis). For example, the device cells 118 each comprise at least two planes of symmetry: a first plane of symmetry being the plane zy that vertically divides each device cell 118 and a second plane of symmetry being the plane zx that divides horizontally in two each device cell 118.
    [0016] The MOSFET device cells 118 shown in FIG. 7 each include an N + doped area 121, which separates the CSSC 22 areas from the channel area 122 in each of the MOSFET device cells 118. The cells 118 of MOSFET devices 118 also include a JFET 124 surrounding the channel areas 122. Unlike the MOSFET device cells 46 shown in FIGS. 3A, 3C and 6, the MOSFET device cells 118 shown on FIGS. Fig. 7 has an elongate hexagonal shape (eg stretched or enlarged) and a honeycomb arrangement of the cells, thereby reducing the electric field near the angles of the well areas P 18, and only in gate oxide 24 above the center of the JFET zone. The CSSCs 22 and the underlying SCCP areas 50 reduce the spacing 123 of the devices 15 compared to other hexagonal device cell arrangements that do not utilize the present CSSC designs. Figure 8 is a top view or plan view of a semiconductor substrate 70 which further comprises another embodiment of the 72D arrangement of devices at CSSC.
    [0017] The arrangement 72D of CSSC devices illustrated in FIG. 8 comprises a number of rectangular cells 130 of MOSFET devices arranged with a particular offset 132 relative to each other, each comprising a segmented source and body contact (CSSC). 134. The horizontal spacing 133 and the vertical spacing 135 of the arrangement 72D of CSSC devices are also illustrated in FIG. 8. In the illustrated embodiment, the SCCS 134 is surrounded by a doped zone 136. N + which separates the SCCC 134 from the P channel area 138 in each of the cells 130 of MOSFET devices. The illustrated MOSFET device cells 130 also include a JFET 140 area surrounding the P-channel regions 138.
    [0018] Each of the SCCS 134 shown in FIG. 8 includes a body contact segment 134A disposed on the side (eg adjacent to or in the immediate vicinity) of a source contact segment 134B of the SCCS 134. The segment 137C 134C is located on less than all sides (eg does not completely surround, is arranged on one side, on less than two sides, on less than three sides) of the 134A of the SCCS 134. Likewise, under each SCCS 134, the underlying CSSC area (not shown) comprises a source contact area that is disposed on less than all sides (eg does not completely surround, is arranged on one side, on less than two sides, on less than three sides) of the body contact area. In addition, the device cells 130, the SCCs 134, and the underlying CSSC area (not shown) of the device arrangement 72D may be referred to as off-center in that the body contact segment 134A (and the underlying body contact zone) is not disposed at the center of the device cells 130. In addition or alternatively, these elements may be termed asymmetric in that the device cells 130, the SCCs 134, and the underlying CSSC area (not shown) of the device arrangement 72D have less than two planes of symmetry arranged perpendicular to the plane of the surface of the semiconductor (that is to say arranged on the z axis). The device cells shown 130 each comprise a single plane of symmetry, which is arranged in the plane z-y which divides each of the device cells 130 into two. Fig. 9 is a top view or plan view of a semiconductor substrate 70 which further comprises another embodiment of the arrangement 72E of devices at CSSC.
    [0019] Arrangement 72E of CSSC devices illustrated in Figure 9 includes a number of elongate (eg stretched or enlarged) hexagonal cells 150 of MOSFET devices disposed at a particular spacing 152. Vertical spacing 153 Arrangement 72E of CCSC devices is also illustrated in Fig. 9. Like the MOSFET device cells 130 of Fig. 8, each of the MOSFET device cells 150 shown in Fig. 9 includes the SCCC 134. Each SCCC 134 comprises a body contact segment 134A disposed on the side (eg adjacent or in the immediate vicinity) of a source contact segment 134B of the SCCS 134.
    [0020] As described above, the source contact segment 134B of the SCCS 134 is disposed on less than all sides (eg does not completely surround, is disposed on one side, on less than two sides, on less than three sides) of the body contact segment 134A for each of the represented CSSCs 134. Similarly, under each SCCC 134, the underlying CSSC area (not shown) includes a source contact area that is arranged on less than all sides (eg not completely surrounded, on one side, on less than two sides, on less than three sides) of the body contact area.
    [0021] In addition, the device cells 150, the SCCs 134 and the underlying CSSC area (not shown) of the device arrangement 72E may be referred to as off-center in that the body contact segment 134A (and the underlying body contact zone) is not disposed at the center of the cells 150 of devices. In addition, or alternatively, these elements may be termed asymmetric in that the device cells 150, the SCCs 134, and the underlying CSSC area (not shown) of the device arrangement 72E have less two planes of symmetry arranged perpendicular to the plane of the surface of the semiconductor (that is to say arranged on the z axis). The device cells 150 represented in fact each comprise a single plane of symmetry, which is arranged in the plane z-y which divides each of the cells 150 of devices in two. In the arrangement 72E illustrated in FIG. 9, the SCCC 134 is surrounded by an N + doped zone 154 which separates the CSSC 134 area from the P channel area 156 in each of the MOSFET device cells 150. The MOSFET device cells shown 150 also include a JFET area 158 surrounding the P channel areas 156. In some embodiments, the hexagonal cells 150 of MOSFET devices 10 shown in FIG. 9 and the "nesting" arrangement. bees "of cells reduce the electric field near the angles of the well areas P 18, as well as in the gate oxide 24 above the center of the JFET zone, as illustrated in FIGS. 4 and 5. in addition, the SCCS 134 makes it possible to reduce the spacing 153 of the devices relative to other hexagonal cell arrangements of devices that do not utilize the present types of CSSCs. Figure 10 is a top view or plan view of a semiconductor substrate 70 which further comprises another embodiment of the 72F arrangement of devices at CSSC. The arrangement 72F of CSSC devices illustrated in FIG. 10 includes a number of square cells 160 of MOSFET devices arranged at a particular mutual offset 162. The horizontal spacing 161 and the vertical spacing 163 of the 72F arrangement CSSC devices are also illustrated in Figure 10. Each of the device cells 160 includes a segmented source and body contact (CSSC) 164 disposed on an area (not shown) of segmented source and body contact (CSSC). The CSSCs 164 are surrounded by an N + doped zone 168 which separates the CCSC zone 164 from the P channel zone 170 in each of the MOSFET device cells 160. The MOSFET cells shown 160 also include a JFET area 172 surrounding the P channel areas 170. The CSSC 164 shown in FIG. 10 each comprise a body contact segment 164A disposed on the side 5 (e.g. adjacent or in the immediate vicinity) of a source contact segment 164B. The source contact segment 164B of the CSSC 164 is disposed on less than all sides (eg does not completely surround, is arranged on one side, on less than two sides, on less than three sides, on less than four sides) of the body contact segment 164A of the SCCS 164. In particular, the CSSC 164 of FIG. 10 comprise a body contact segment 164A in contact with two sides of which there is a source contact segment 164B in which "L". That is, the source contact segment 164B only partially surrounds or encapsulates the body contact segment 164A for each CSSC 164. In some embodiments, the square cells 160 of MOSFET devices shown in FIG. may have advantages over other forms of MOSFET device cells (eg, designs without the CSSC area 164) because of the enlarged periphery of the channel area 170 and / or the increased density of the JFET area 172. In addition, device cells 160, CSSC 164, and underlying CSSC areas (not shown) of device arrangement 72F may be referred to as off-center in that segments of body contact 164A (and the underlying body contact zone) are not disposed at the center of the cells 160 of devices. In addition or alternatively, these elements may be termed asymmetric in that the device cells 160, the CSSC 164 and the underlying CSSC area 30 (not shown) of the device arrangement 72F have less than two planes of symmetry arranged perpendicularly to the plane of the semiconductor surface (i.e. arranged on the z-axis). The device cells 150 each comprise in fact a single plane of symmetry, which is arranged along the z-axis which divides diagonally each of the cells 160 of devices. Fig. 11 is a top view or plan view of a semiconductor substrate 70 which further comprises another embodiment of the arrangement of CSSC devices. The 72G arrangement of CSSC devices illustrated in FIG. 11 includes a number of hexagonal cells 180 of MOSFET devices, each comprising a segmented source and body contact (CSSC) 182. In addition, the MOSFET device cells 180 Arrangements 72F of CSSC devices are arranged at a particular mutual offset 183 (e.g., the horizontal spacing is equal to the vertical spacing in a regular hexagonal shape). In the illustrated embodiment, each of the CSSC 182 is surrounded by an N + doped area 188 that separates the CCSC 182 from the channel area 190 in each of the MOSFET device cells 180. The MOSFET device cells 20 shown 180 also include a JFET area 192 surrounding the P channel areas 190. The CSSC 182 shown in FIG. 11 each comprise a side-disposed body contact segment 182A (e.g. adjacent or proximate) of a source contact segment 182B. The source contact segment 182B of the CSSC 182 is disposed on less than all sides (eg does not completely surround, is disposed on one side, on less than two sides, on less than three sides or on less than four sides) of the body contact segment 182A of the SCCS 182. The shape and arrangement of the CSSC 182 of Fig. 11 are shown only as examples. For example, as illustrated, the CSSCs 182 are placed at the center of each hexagonal device cell 180 and include a kite-shaped body contact segment 182A and a chevron source contact segment 182B. In other embodiments, the shape and / or relative dimensions of the body contact segment 182A and the source contact segment 182B may be different depending, for example, on the requirements of the contact resistance and to the design of the devices. On the other hand, in some embodiments, hexagonal cells 180 of MOSFET devices 10 shown in FIG. 11 may provide advantages over rectangular or square cells 46, 130 and 160 of MOSFET devices due to the enlarged periphery of the MOSFET devices. channel area 190 and / or the increased density of the JFET area 192. The device arrangement 72G reduces the electric field near the angles of the well areas P 18, as well as in the gate oxide 24. above the center of the JFET area. In addition, the CSSC 182 makes it possible to reduce the spacing of the devices relative to other hexagonal cell arrangements of devices that do not use the present types of CSSCs.
    [0022] In addition, the device cells 180, the underlying CSSC 182 and CSSC areas (not shown) of the device arrangement 72G may be referred to as off-center in that the body contact segment 182A (and the underlying body contact zone) are not disposed at the center of the device cells 180. In addition or alternatively, these elements may be termed asymmetric in that the device cells 180, the SCCs 182 and the underlying CSSC area (not shown) of the device arrangement 72G have less two planes of symmetry arranged perpendicular to the plane of the surface of the semiconductor (that is to say arranged on the z axis). The device cells represented 180 each comprise in fact a single plane of symmetry, which is arranged along the z-axis which divides diagonally each of the cells 180 of devices. The described embodiments 72A-G of cellular arrangements of CSSC devices provide performance advantages over other device arrangements and other device cell designs. By way of comparison, an example of another arrangement of devices is illustrated in FIG. 12A, which is a top view or a plan view of an array 194 of device bands (thus a non-cellular arrangement). The strip arrangement 194 shown in Figure 12A includes: channel areas 195, N + areas 196, source contact areas 197, body contact areas 198, and a JFET 199 area. Contact areas and the body contact areas 198 are in the form of continuous strips on the surface of the semiconductor in the strip arrangement 194 shown in FIG. 12A. An example of another arrangement of devices is shown in Figure 12B, which is a top view or a plan view of an arrangement 200 of ladder band devices (thus a non-cellular arrangement) with source contacts. segmented bodies. The illustrated arrangement 200 includes: channel regions 202, N + zones 204, segmented source / body contacts 206 (including the body contact segment 206A and the source contact segment 206B), and the JFET area 210. Fig. 12B also shows dimensions of the ladder array device arrangement 200, including: channel length (Lch 212), channel distance and ohmic area (Lch-to-ohm 214), ohmic area width (Wohm 216), width of the JFET area (WJFET 218), length of the source contact area segment (Ln 220), length of the body contact area segment (Lp222 ), the device surface subset (ACeii 224, represented by the dotted rectangle 224), the JFET area in Aceii 224 (AJFET 226, represented by the hatched area 226), and the channel width ( Wch 228) in Acell 224 for the arrangement 200 of ladder band devices 5 shown. By way of further comparison, another exemplary device arrangement is illustrated in Figure 12C, which is a top view or a plan view of a cellular cell device arrangement 240 without source / body contacts. segmented. The cell arrangement 240 of square cell devices 10 includes: channel regions 242, N + zones 244, body contact 246, source contact 248 and JFET zones 250. FIG. 12C also gives dimensions of the cell arrangement 240 of square cell devices, including: the channel length (Lch 252), the distance between the channel and the ohmic area (Lch_to_ohp, 254), the width of the ohmic area (Wohm 256), the JFET area width (WJFET 258), the half-width of the source contact area (Wp / 2 260), the width of the body contact sone (Wp 262), the device cell surface shown by the dashed rectangle 264), the JFET area per cell (AJFET, represented by the hatched area 266), and a quarter of the width of the inner channel (Wch / 4,268; Wch = 4Wch / 4) for the cell illustrated by the cell arrangement 240 of square cell devices. In view of the foregoing, the embodiments of the cellular arrangement 72A-G of CSSC devices provide performance advantages over other device arrangements and other device cell designs by enabling channel width (eg larger channel circumference) larger than in other arrangements of devices. For example, equation 1 describes a ratio of the channel width (Wch) resulting from the cell arrangement 72A of CSSC devices according to the present invention (indicated by the "CSSC" index) shown in Figs. 3A. and 3C at the channel width 228 provided by the "ladder" strip arrangement 200 (indicated by the "band" index) of Figure 12B. Equation 1 is obtained and simplified by assuming the same design rules and technological limitations (eg Lch, Lch to ohm, Wohm, WJFET, Wn and Wp) for the two compared designs. From equation 1 can be derived the inequality of equation 2 which mathematically demonstrates the dimensions of devices for which the channel width (Wch) provided by the cellular arrangement of devices according to the present invention, having CSSC (i.e., Wch cssc) is larger than the channel width 228 provided by the "ladder" strip arrangement 200 of Figure 12B (i.e. Wch Band).
    [0023] In another example, equation 3 describes a ratio of the channel area density (Wch) provided by the cellular arrangement 72A of CSSS devices according to the present invention (indicated by the "CSCC" index) to the channel width (eg 4 * Wch / 4,268) provided by the "ladder" strip arrangement 200 (indicated by the "SC" index) of Figure 12C. Equation 3 is obtained and simplified assuming the same design rules and technological limitations (eg Lch, Lch to ohm, Wohm, WJFET, Wn and Wp) for the two compared designs. From Equation 3 can be derived the inequality of Equation 4 which mathematically demonstrates the device dimensions for which the channel width (Wch) provided by the cellular arrangement 72A of CSSC devices according to the present invention (FIG. that is, Wch cssc) is larger than the channel width 268 provided by the square cell cell arrangement 240 of Fig. 12B (i.e. Wch sc).
    [0024] 3022685 Eq.
    [0025] 1 W chCSSC 4 Lch-to-ohm + Wn + Wp + Wohm Eq.
    [0026] 2 WchCSSC> Wchgande if 2 Lch-to-ohm Wohm> 2 Lai WJFET 5 Eq.
    [0027] 3 W chCSSC = W chsc ((2 Lch-to-ohm + Wn + Wp + 2 Lat + VII, JFETcssC) - (2 Lcn_tp_ohm + Wohm + 2 Lch + WJFET) ((2 LCh-tO-Ohni Wp 2 Lch WIFET ) 2) Eq.
    [0028] 4 Wcncssc> Wchsc if (4 Lch-to-ohm Wn Wp + Wohm) - (2 Lat + 2 Lch-to-ohm Wn Wp WJFET)> 2 - (2 Lcn_tp_ohm + Wn Wp) - (2 Lat + 2 Lch- Embodiments 72A-G of cellular arrangements of devices according to the present invention may also provide performance advantages over other device arrangements and other device cell designs. ensuring a density of the JFET area larger than that of other arrangements of devices For example, equation 5 describes a ratio of the density of the JFET zone (eg illustrated as AJFET 78 divided by Acell 76 in Fig. 3C) provided by the cellular arrangement 72A of CSSC devices according to the present invention (designated by the "CSSC" index) at the density of the JFET area (eg illustrated as AJFET 226 divided by Acell 224 in FIG. 12B) provided by the "ladder" strip arrangement 200 (designated the "Band" index) Equation 5 is obtained and simplified by assuming the same rules of W chbandVITJFET + 2 Lch + 2 Lcn_ to -ohm + Wn + Wp (2 Lcn_tp-ohm Wn Wp) + (2 Lcn_tp_ohm Wohm) (2 Lch-to-ohm Wn Wp) - 2 3022685 36 design and the same technological limitations (eg. Lch, Lch to ohm, Wohm, WJFET, Wn and Wp) for the two compared designs. From equation 5 can be derived the inequality of equation 6 which mathematically demonstrates the device dimensions for which the density of the JFET area provided by the cellular arrangement 72A of CSSC devices according to the present invention (FIG. ie DJFET cssc) is larger than the density of the JFET area provided by the ladder band arrangement 200 of Figure 12B (i.e., DJFET Band).
    [0029] In another example, equation 7 describes a ratio of JFET area density (eg, illustrated as AJFET 78 divided by Acell 76 in FIG. 3C) provided by device cell arrangement 72A. to CSSC according to the present invention (denoted by the "CSSC" index) at the density of the JFET area (eg illustrated as AJFET 266 divided by Acell 264 in Fig. 12C) provided by the arrangement 240 square cell cell (denoted by the index "SC"). Equation 7 is obtained and simplified assuming the same design rules and technological limitations (eg Lch, Lch to ohm, Wohm, WJFET, Wn and Wp) for the two compared designs. From equation 7 can be derived the inequality of equation 8 which mathematically demonstrates the device dimensions for which the density of the JFET area provided by the cellular arrangement 72A of CSSC devices according to the present invention (FIG. that is, DJET cssc) is larger than the JFET density provided by the square cell cell arrangement 240 of Figure 12C (i.e., DJFET SC). In equations 5 to 8, the conduction via the angle channel zone is not taken into account, which is a valid assumption whenever (2Lch-to-ohm Wohm) is much greater than Lch.
    [0030] Eq.
    [0031] 5 D JFET CSSC 4 Lch + 4 Lch-to-ohm + Wn + Wp + Wohm WJFET ai DJFET band W + 2 L + 2 Lai_ to-ohm + Wn + Wp 3022685 37 Eq.
    [0032] 6 DJFET> D IFETBand Si (2 Lch-to-ohm + Wohm)> WJFET 5 Eq.
    [0033] 7 DJFET D JFET sc (2 Lch-to-ohm + Wn + Wp + 2 Lch) + (2 Lch-to-ohm (2 Lch-to-ohm + Wn + Wp + 2 Lch + WJFET). (2 Lch -to-ohm ((2 Lch-to-ohm + Wn + Wp + 2 Lm) - 2 (2L + Wn + Wp + 2 Lch + W 2 JFET) Eq.
    [0034] 8 DJFETCSSC> DJFETsc If (4 Lch_tp_phm + Wn + Wp + Wohm) - (2 Lm + 2 Lch-to-ohm + Wn + Wp + WJFET)> 2 (2 Lch_tp_ohm + Wn + Wp) - (2 Lm + 2 Lch Figure 13 is a graph 280 illustrating Equation 1 (i.e., the channel width (Wch) of the cell arrangement 72A of CSSC devices of Figure 3C normalized to the width of the 228 of the ladder array arrangement 200 of Figure 12B) for devices with three different channel lengths, in particular, the graph 280 shown in FIGURE 13 includes a curve 282 representing channel (Lch) of 0.3 μm, a curve 284 representing channel length devices (LCH) of 0.5 μm and a curve 286 representing channel length devices (LCH) of 0.7 μm. for the curves 282, 284 and 286 represented: Lch-to-ohm = 1.3 iam, Wohm = 1.6 iam, Wp = 3 tm and Wp = 3 pm In this way, the curves s 282, 284 and 286 illustrate the increased channel width (Wch) allowed by the arrangement 72A of the CSSC devices of FIG. 3C with respect to the channel width 228 of the arrangement 200 of + Wohm + 2 Lm) + Wohm + 2 Lm + WJFET) 3022685 38 ladder band devices of Figure 12B. For example, in some embodiments, as illustrated in Figure 13, the arrangement 72A of CSSC devices may allow a channel width greater than about 1% to about 40% of the channel width of the arrangement. 200 of ladder band devices. Fig. 14 is a graph 290 illustrating equation 5 (i.e. JFET density of cell arrangement 72A of CSSC devices of Fig. 3C normalized to JFET density of ladder device arrangement 200; of Figure 12B) for devices with three different channel lengths. In particular, the graph 290 shown in Fig. 14 includes a curve 292 representing channel length devices (Lch) of 0.3 μm, a curve 294 representing channel length devices (LCH) of 0.5 μm and a curve 296 representing channel length devices (Lch) of 0.7 μm. For the curves 292, 294 and 296 shown: Lch-to-ohm = 1.3 iam, Wohm = 1.6 iam, Thus, curves 292, 294, and 296 illustrate the increased JFET density (DJFET) enabled by the cellular arrangement 72A of CSSC devices of FIG. 3C with respect to FIGS. arrangement 200 of ladder band devices of Figure 12B. For example, in some embodiments, as illustrated in FIG. 14, the arrangement 72A of CSSC devices may allow a JFET density greater than about 1% to about 60% of the JFET density of the arrangement. 200 of ladder band devices. Fig. 15 is a graph 300 illustrating equation 3 (i.e., channel width (Wch) of cellular arrangement 72A of CSSC devices of Fig. 3C normalized to channel width 268 of cellular arrangement 240 to square cells of Figure 12C) for devices with three different channel lengths. In particular, the graph 300 shown in Fig. 3022685 includes a curve 302 representing channel length devices (Lch) of 0.3 μm, a curve 304 representing channel length devices (Lch) of 0. , 5im and a curve 306 representing channel length devices (Lch) of 0.7μm. Moreover, for the curves 302, 304 and 306 shown: Lch-to-ohm = 1.3 i.tm, Wohn = 1.6 i.tm, Wn = 1.6 i.tm and Wp = 1, 6 i.tm. In this way, curves 302, 304 and 306 of FIG. 15 illustrate the increased channel width (Wch) enabled by the arrangement 72A of the CSSC devices of FIG. 3C (with respect to the channel width 268 of FIG. For example, in some embodiments, as shown in Figure 15, the arrangement 72A of devices to CSSC may allow a channel width greater than about 1%. at approximately 15% to the channel width of the cell arrangement 240 of square cell devices Figure 16 is a graph 310 illustrating Equation 7 (ie the JFET density of the cell arrangement 72A of devices at SCCS of Figure 3C normalized to the JFET density of the square cell device arrangement 240 of Figure 12C) for devices with three different channel lengths, in particular, the graph 310 shown in Figure 16c. renders a curve 312 representing channel length devices (Lch) of 0.3 μm, a curve 314 representing 0.5 μm channel length devices (Lch) and a curve 316 representing channel length (Lch) of 0.7 i.tm. On the other hand, for curves 312, 314 and 316 represented: Lch-to-ohm = 1.3 i.tm, Wohn = 1.6 i.tm, Wn = 1.6 i.tm and Wp = 1.6 i.tm. In this way, curves 312, 314 and 316 of FIG. 16 illustrate the increased JFET density (DJFET) enabled by the cellular arrangement 72A of the CSSC devices of FIG. 3C with respect to the arrangement 240 of FIGS. square cells of Figure 12C. For example, in some embodiments, as shown in Figure 14, the arrangement 72A of devices to CSSC may allow a JFET density greater than about 1% to about 20% of the JFET density of the arrangement. 240 of square cell devices.
    [0035] The technical effects of the invention include device designs and cellular arrangements that improve the performance of semiconductor devices. In particular, the present embodiments reduce conduction losses of the devices (eg, strongly limit Rds (on)) by providing increased channel width and / or increased channel density to reduce channel resistance and providing an increased JFET density to reduce the component resistance of the JFET zone. The present embodiments provide these advantages, at least in part, by utilizing a cellular arrangement of segmented source and body contact devices (CSSC) in which a body contact area is only partially (i.e. incompletely, not on all sides) surrounded by one or more source contact areas. The cellular arrangements 72A-G to CSSC according to the invention make it possible to reduce the spacing of the devices and, thus, to increase the channel width per unit area and / or to increase the density of the JFET zone. Furthermore, the present invention can reduce conduction losses in a number of different device structures (eg, UMOSFET, VMOSFETs, TBGIs, IBMCTs or any other suitable device) and / or different semiconductors (eg SiC, Si, Ge, AlN, GaN, GaAs, C or any other suitable semiconductor substrate).
    权利要求:
    Claims (15)
    [0001]
    REVENDICATIONS1. A system, comprising: a semiconductor device cell (46, 118, 130, 150, 160, 180) disposed on a surface of a silicon carbide (SiC) semiconductor layer (2), the cell (46, 118 , 130, 150, 160, 180) of a semiconductor device comprising: a migration zone (16) having a first conductivity type; a well area (18) having a second conductivity type, disposed in the immediate vicinity of the migration zone (16); a source zone (20) having the first conductivity type disposed in the immediate vicinity of the well area (18); a channel region (28, 47, 48, 122, 156, 170, 190) having the second conductivity type, disposed in the immediate vicinity of the source area (20) and close to the surface; and a body contact area (44) having the second conductivity type, disposed over a portion of the well area (18), the body contact area (44) being substantially disposed at the center of the cell ( Semiconductor device (46, 118, 130, 150, 160, 180), and a segmented source and body contact (CSSC) (22, 134, 164, 182, 206) disposed over a portion of the surface, the CSSC (22, 134, 164, 182, 206) comprising: a body contact segment (22A, 134A, 164A, 182A, 206A) disposed over the body contact area (44) substantially in the center of the semiconductor device cell; and 3022685 42 at least one source contact segment (22B, 134B, 164B, 182B, 206B) disposed in the immediate vicinity of the body contact area (44) and over a portion of the source area (20) the source contact segment (s) (22B, 134B, 164B, 182B, 206B) not completely surrounding the body contact segment (22A, 134A, 164A, 182A, 206A) of the SCCS (22 , 134, 164, 182, 206).
    [0002]
    The system of claim 1, wherein the CSSC (22, 134, 164, 182, 206) has at least two distinct planes of symmetry perpendicular to the surface. 10
    [0003]
    The system of claim 1, wherein a portion of the segment of the body contact zone (44) is not disposed under the SCCS (22, 134, 164, 182, 206), and wherein the portion of the body contact zone (44) has a width greater than or equal to about 10% and less than or equal to about 50% of a width of the CSSC (22, 134, 164, 182, 206).
    [0004]
    The system of claim 1, wherein one or more components of the semiconductor device cell (46, 118, 130, 150, 160, 180) has at least partially a misalignment or misalignment. shape due to manufacturing imperfections.
    [0005]
    The system of claim 1, wherein the CSSC (22, 134, 164, 182, 206) comprises at least two body contact segments (22A, 134A, 164A, 182A, 206A) arranged on either side of the body contact segment (22A, 134A, 164A, 182A, 206A).
    [0006]
    The system of claim 5, wherein the at least two body contact segments (22A, 134A, 164A, 182A, 206A) are not fully isolated from each other by the body contact segment ( 22A, 134A, 164A, 182A, 206A). 30
    [0007]
    The system of claim 1, wherein the CSSC (22, 134, 164, 182, 206) has an elongated rectangular shape. 3022685 43
    [0008]
    The system of claim 1, wherein the channel region (28, 47, 48, 122, 156, 170, 190) has an elongated hexagonal shape.
    [0009]
    The system of claim 1, wherein the semiconductor device cell (46, 118, 130, 150, 160, 180) comprises a field effect transistor (FET), an insulated gate bipolar transistor (IGBT). , an isolated base MOS control thyristor (IBMCT), a junction field effect transistor (JFET) or a metal-semiconductor field effect transistor (MESFET).
    [0010]
    A system, comprising: a cellular arrangement (72A, 72B, 72C, 72D, 72E, 72F, 72G) of semiconductor devices comprising a plurality of semiconductor device cells (46, 118, 130, 150, 160, 180); disposed on a surface of a semiconductor layer (2) of silicon carbide (SiC), the plurality of cells (46, 118, 130, 150, 160, 180) of semiconductor devices having a cell arrangement each comprising: migration (16) having a first type of conductivity; a well region (18) having a second conductivity type disposed in the immediate vicinity of the migration zone (16), the well area (18) comprising a body contact area (44) disposed close to the surface ; A source area (20) having the first conductivity type disposed in the immediate vicinity of the well area (18), the source area (20) including a source contact area (42) disposed proximate the surface and close to the body contact area (44); and a segmented symmetrical source and body contact (CSSC) (22, 134, 164, 182, 206) disposed over a portion of the surface, the asymmetric CSSC (22, 134, 164, 182, 206) comprising: a body contact segment (22A, 134A, 164A, 182A, 206A) disposed over the body contact area (44) of the cell (46, 118, 130, 150, 160, 180) of semiconductor device; and at least one source contact segment (22B, 134B, 164B, 182B, 206B) disposed in the immediate vicinity of the body contact segment (22A, 134A, 164A, 182A, 206A) and over the contact area of source (20) of the semiconductor device cell (46, 118, 130, 150, 160, 180), the source contact segment (s) (22B, 134B, 164B, 182B, 206B) not completely surrounding the body contact segment (22A, 134A, 164A, 182A, 206A)
    [0011]
    The system of claim 10, wherein the cellular arrangement (72A, 72B, 72C, 72D, 72E, 72F, 72G) of semiconductor devices is designed such that (2 Lch-to-ohm + Wohm) is greater than at (2 Lch-to-ohm + WJFET) or so that (2 Lchto-ohm + Wohm) is greater than WJFET), or so as to combine the two, Lch being a channel length, Lch-to-ohm being the length of an ohmic zone, Wolin being the width of the ohmic zone and WJFET being the width of a JFET zone (48, 124, 140, 158, 172, 92, 199, 210, 218) of the plurality of cells (46, 118, 130, 150, 160, 180) of semiconductor devices having a cellular arrangement. 25
    [0012]
    The system of claim 11, wherein the cellular arrangement (72A, 72B, 72C, 72D, 72E, 72F, 72G) of semiconductor devices provides a greater channel width (Wch), or higher density of JFET (DJFET), or a combination thereof, that a strip semiconductor device arrangement having the same Lch, Lch-to-ohm, Wohm, and WJFET as the cellular arrangement (72A, 72B, 72C). , 72D, 72E, 72F, 72G) of semiconductor devices.
    [0013]
    The system of claim 10, wherein the cellular arrangement (72A, 72B, 72C, 72D, 72E, 72F, 72G) of semiconductor devices is designed such that ((4 Lch-to-ohm + Wn + Wp + Wohm) (2 Lch + 2 Lch-to-ohm + Wn + Wp + WJFET)) greater than (2 - (2 Lch-to-ohm + Wn + Wp) - (2 Lch + 2 ', ch -Io-ohm + Wohm WJFET)) or so that ((4 Lch + Leh_to ohni Wn Wp Wohm) - (2 Lch + 2 Lch-to-ohm + Wn + Wp + WJFET)) is greater than (2 - ( 2 Lch 10 + 2 Lch-to-ohm + Wn + Wp) - OR (2 Lch + 2 Lch-to-ohm + Wohm + WJFET)), OR to combine the two, Lei, (52, 212, 252) being the channel length, Leh to_ohm (54, 214, 254) being the length of the ohmic zone, Woh ', (56, 216, 256) being the width of the ohmic zone, Wn (42, 58) being the width of the source contact area (20), Wp (60, 262) being the width of the body contact area (44) and WJFET (73, 218) being the width of a JFET area (48, 124, 140, 158, 172, 92, 199, 210, 218) of the plurality of this llules (46, 118, 130, 150, 160, 180) of semiconductor devices with cellular arrangement. 20
    [0014]
    The system of claim 13, wherein the cellular arrangement (72A, 72B, 72C, 72D, 72E, 72F, 72G) of semiconductor devices has a larger channel width (Wch) or higher JFET density. (DJFET), or a combination thereof, than a different arrangement of semiconductor devices having the same Lch, Lch-to-ohm, Wohm, Wn, Wp and WJFET as the cellular arrangement (72A, 72B, 72C, 72D, 72E, 72F, 72G) of semiconductor devices, the different arrangement of semiconductor devices being devoid of CSSC.
    [0015]
    The system of claim 10, wherein the cellular arrangement (72A, 72B, 72C, 72D, 72E, 72F, 72G) of semiconductor devices comprises the plurality of cells (46, 3022685, 46, 118, 130, 150, 160, 180) of semiconductor devices arranged in rows and / or columns.
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    同族专利:
    公开号 | 公开日
    CN105206673A|2015-12-30|
    US10192958B2|2019-01-29|
    US20150372088A1|2015-12-24|
    GB201511043D0|2015-08-05|
    JP6782062B2|2020-11-11|
    FR3022685B1|2019-11-01|
    GB2529930A|2016-03-09|
    JP2016009866A|2016-01-18|
    GB2529930B|2018-10-31|
    BR102015015124A2|2017-05-16|
    CA2894143A1|2015-12-24|
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    优先权:
    申请号 | 申请日 | 专利标题
    US14/313785|2014-06-24|
    US14/313,785|US10192958B2|2014-06-24|2014-06-24|Cellular layout for semiconductor devices|
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